An integrated circuit or chip has input/output (I/O) connections in order to function as an electronic circuit. Many of these chips have more than 200 I/O connections. These I/O connections are attached, e.g., soldered, to a printed wiring board (PWB) or a printed circuit board (PCB).
In conventional packaging using peripheral-leaded surface mounted packages, such as peripheral leaded QFPs (Quad Flat Packs), wire bonding to a metallic lead frame is used to connect the I/Os of the IC chip to the I/Os of the QFP. The I/Os of the QFP are distributed along the periphery of the QFP. The maximum number of QFP I/Os distributed along the QFP periphery is limited to prevent the spacing between adjacent QFP I/O leads from becoming so small as to pose a potential electrical shorting problem during solder reflow at board mounting. FIGS. 1a and 1b illustrate a typical QFP, known as PQFP (Plastic Quad Flat Pack) 10, showing the pins or leads 15 that are bent to extend horizontally from the periphery of the PQFP.
For high I/O count IC chips, Ball grid array (BGA) packages have been used that can have more I/Os than QFPs. BGAs connect to PWBs or PCBs using balls instead of pins or leads. Typically, the I/O interconnects of the IC chip are brought out to land sites arranged in an array pattern on the bottom face of the substrate of the BGA package. Solder bumps or balls are attached to these land sites. These solder bumps or balls, in turn, provide the I/O connections of the BGA package. (IC packages utilizing such solder bumps or balls are described in the above-identified related applications.) Such a configuration allows an increase in the number of I/O interconnects over conventional QFP packages, in which the I/O interconnects are distributed along the periphery of the QFP package.
FIG. 2a shows a typical BGA package 20 with an overmolded encapsulant 25. A silicon IC chip 30 is mechanically attached to a substrate 35 via a die attach 40. The overmolded encapsulant 25 covers the chip 30 and portions of the top surface 45 of the substrate 35. As in conventional QFP packaging, the interconnect from the silicon IC chip 30 to the substrate 35 is typically by wire bonds 50.
The I/Os of the chip 30 are routed to the bottom surface 55 of the substrate 35 through metal conductors (not shown) embedded in the substrate 35. I/Os of the chip 30 are connected to these embedded conductors by the bond wires 50. In addition, through going vias 60, and thermal vias 65 used for heat transfer, may also be formed between the top and lower surfaces 45, 55 of the substrate 35. The going-through vias 60 may be interconnect vias, and may serve to relieve mechanical stress.
The I/Os of the BGA package 20 are an array of solder balls 70 located at the bottom surface 55 of the substrate 35. FIG. 2b shows a bottom view of the BGA package 20, wherein the array of solder balls 70 attached to the bottom surface 55 is shown.
The size of the BGA package 20 is considerably larger than the size of the IC chip 30. This is mainly due to the substrate 35. More advanced BGA packages have a small sized substrate due to the use of flip-chip type of chip-to-substrate interconnects, in lieu of wire bonding. FIGS. 3 and 4 show such smaller sized BGA packages, sometimes referred to in the industry as micro-BGA packages.
FIG. 3 shows a plastic BGA package 80 with a solder bumped flip chip. The IC chip 30 is connected to the substrate 35 via an array of solder balls 85 located between the bottom surface of the IC 30 and a portion of the upper surface 45 of the substrate 35. The remaining portion of the upper surface 45 of the substrate 35 is covered by an insulated plated copper conductor 90. The array of solder balls 85 is encapsulated by an underfill encapsulant compound 95.
The array of BGA solder balls 70, attached to the bottom surface 55 of the substrate 35, is used to connect the BGA package 80 to the PWB (Printed Wire Board) or PCB (Printed Circuit Board) (not shown). The portion of the bottom surface 55 not covered by the array of BGA solder balls 70, is covered by a layer of solder mask 100. The substrate 35 may have signal/ground vias 105 between the insulated plated copper conductor 90 and the layer of solder mask 100. In addition, the substrate 35 may have thermal/ground vias 110 between the underfill encapsulant compound 95 and the layer of solder mask 100.
FIG. 4 shows another BGA package known as SLICC (Slightly Larger than IC Carrier) BGA package 120 from Motorola. The SLICC BGA package 120 has a small SLICC substrate 35 which may be an organic interface. The SLICC substrate 35 is slightly larger in area than the IC chip 30. The IC chip 30 is connected to the substrate 35 by interconnections sometimes known as C4 interconnections 125, which are encapsulated by an underfill compound 95. FIG. 4 also shows a PCB 130 (or PWB) upon which the array of BGA solder balls 70 is attached.
The continuous quest for smaller IC packages has led to the introduction of a class of packages known as chip-sized packages (CSPs). These CSP packages have form factors marginally larger than the size of the silicon IC chip. In CSP packages, a substrate is not necessary. This allows the CSP package form factor to be further reduced such that it is only marginally larger than the IC chip itself. Several configurations have been proposed and these are shown in FIGS. 5-9.
FIGS. 5a-5c show a Tessera Compliant Chip (TCC) package 150. As shown in FIG. 5a, the IC chip 30 is attached to an elastomer compliant layer 155 via a flex circuit 160. The elastomer compliant layer 155 has an array of Ni/Au bumps 165 which connects the compliant layer 155 to the substrate 35. The IC chip 30 and flex circuit 160 are encapsulated in an encapsulant compound or casing 175. Alternatively, as shown in FIG. 5b, the IC chip 30 and flex circuit 160 are not encapsulated. FIG. 5c shows the flex circuit 160 and the array of bumps 165 of FIG. 5b in greater detail. The flex circuit 160 comprises fan-in tab leads 175 which extend from the periphery of the compliant layer 155 and connect to pads 180 on the active surface 185 of the chip 30.
FIG. 6 is a fine pitch BGA package 200 from NEC showing the IC chip 30 which is located over an interface layer 205. In turn, the interface layer 205 is mechanically attached to a carrier 210 via an adhesive 215. The interface layer 205 has interface ports 220 which are distributed on the active surface 225 of the chip 30. These interface ports 220 act as the I/Os of the chip 30. The interface ports 220 are electrically connected to carriers protrusions 230 that extend toward the interface ports 220. The carrier 210 has a layer 235 on which bumps and metal lines are deposited to form the protrusions 230, solder bumps 240 and metal lines 245. The solder bumps 240 and the protrusions 230 are on opposite surfaces of the metal lines 245. The solder bumps 240 are in electrical contact with the carriers protrusions 230 through the metal lines 245 and act as the I/O ports of the fine pitch BGA package 200.
FIG. 7 shows a CSP 250 made by Matsushita having the IC chip 30 attached to a ceramic substrate 260 via an array of solder bumps 270. Sealing resin 280 encapsulates the array of solder bumps 270, the sides of the IC chip 30 and the top surface of the substrate 260. The substrate 260 has vertical via holes 290 therethrough. An array of land sites 295 are located at the bottom surface 292 of the substrate 260, onto which solder balls (not shown) may be attached.
FIG. 8 shows a CSP 300 made by Fujitsu which uses a lead frame 310 as the I/Os of the CSP 300. The lead frame 310 is connected to the I/Os of the IC chip 30 by bonding wires 320. A protection film 330 separates and attaches the lead frames 310 to the IC chip 30. Sealing resin 340 encapsulates the sides of the IC chip 30, the wires 320 and portions of the lead frames 310, leaving a lower portion of the lead frames 310 exposed.
FIGS. 9a-9d show a process for making a CSP 400 (FIG. 9d) which is shown in greater detail in FIG. 9e. The CSP 400 is made by Mitsubishi. As shown in FIG. 9a, the IC chip 30 has Pb/Sn solder interconnecting bumps 405 on its active surface 410. The IC chip 30 is mounted on its active surface 410 to a carrier base frame 415 which also has frame bumps 420. The interconnecting bumps 405 of the chip 30 are bonded to corresponding frame bumps 420 of the frame 415. In the mounted position, the inactive surface 425 of the chip 30, which is opposite the active surface 410, is also shown in FIG. 9a.
As shown in FIG. 9b, the bonded chip 30 and portions of the frame 415 are encapsulated with a resin 430 by a molding process identical to that used in conventional molding of IC packages. This is accomplished by placing the chip 30 in a mold 435 having cavities and thereafter pouring resin 430 into the mold 435 to fill the mold cavities. FIG. 9b shows a section of a mold 435 which is used to encapsulate the chip 30 with the resin 430.
Next, as shown in FIG. 9c, the base frame 415 is separated from the encapsulated chip 30 in a way that transfers the frame bumps 420 from the frame 415 to the chip 30. This results in an encapsulated chip 30 that has transferred frame bumps 420 which have exposed lower surfaces 440. Finally, as shown in FIG. 9d, solder balls 450 are attached to the exposed lower surfaces 440 (FIG. 9c) of the transferred frame bumps 420. The solder balls 450 act as external I/O electrodes of the CSP 400.
FIG. 9e shows in greater detail the chip 30 with an external electrode bump 450. The chip 30 has an electrode pad 455 at its active surface 410. Wiring conductors 460, which form a pattern, are connected to the electrode pad 455. The Pb/Sn solder 405 is attached to the wiring conductor 460. The Pb/Sn solder 405 surrounds the transferred frame bump 420. The resin encapsulant 430 covers the active surface 410 of the chip 30, leaving exposed the lower portion 440 of the transferred frame bump 420 whereon the external electrode bump 450 is attached. A polyimide film 470 separates the resin 430 from the wiring conductor 460.
Although the CSPs shown in FIGS. 5a-9e are smaller than the BGAs shown in FIGS. 2a-4, the conventional CSPs and BGAs have complex structures which are costly and difficult to manufacture. Furthermore, some of the conventional CSPs still have a substrate, or a substrate-like structure which is larger than the IC chip itself.
Accordingly, it is an object of this invention to provide a CSP and method for making a CSP in which the substrate and other intermediate processes are eliminated.
Another object of this invention is to provide a CSP which has enhanced miniaturization, due to the absence of the substrate, and thus is truly a chip-size package, having a size which is approximately the same size as the IC chip.
Yet another object of this invention is to provide a CSP and method for making thereof which are less costly and simple to manufacture as all the processes used are established practices in electronic packaging.